Cantitate/Preț
Produs

Introduction to Advanced System-on-Chip Test Design and Optimization: Frontiers in Electronic Testing, cartea 29

Autor Erik Larsson
en Limba Engleză Hardback – 7 noi 2005
SOC test design and its optimization is the topic of Introduction to Advanced System-on-Chip Test Design and Optimization. It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the implementation into EDA (electronic design automation) tools. The book is divided into three sections: i) test concepts, ii) SOC design for test, and iii) SOC test applications. The first part covers an introduction into test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. The second part of the book discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. Finally, the third part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with the core selection process.
Citește tot Restrânge

Toate formatele și edițiile

Toate formatele și edițiile Preț Express
Paperback (1) 93064 lei  43-57 zile
  Springer Us – 2 feb 2011 93064 lei  43-57 zile
Hardback (1) 94840 lei  43-57 zile
  Springer Us – 7 noi 2005 94840 lei  43-57 zile

Din seria Frontiers in Electronic Testing

Preț: 94840 lei

Preț vechi: 115659 lei
-18% Nou

Puncte Express: 1423

Preț estimativ în valută:
18150 18854$ 15077£

Carte tipărită la comandă

Livrare economică 03-17 februarie 25

Preluare comenzi: 021 569.72.76

Specificații

ISBN-13: 9781402032073
ISBN-10: 1402032072
Pagini: 408
Ilustrații: XX, 388 p.
Dimensiuni: 156 x 232 x 27 mm
Greutate: 1.09 kg
Ediția:2005
Editura: Springer Us
Colecția Springer
Seria Frontiers in Electronic Testing

Locul publicării:New York, NY, United States

Public țintă

Professional/practitioner

Cuprins

Testing Concepts.- Design Flow.- Design for Test.- Boundary Scan.- SOC Design for Testability.- System Modeling.- Test Conflicts.- Test Power Dissipation.- Test Access Mechanism.- Test Scheduling.- SOC Test Applications.- A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling.- An Integrated Framework for the Design and Optimization of SOC Test Solutions.- Efficient Test Solutions for Core-Based Designs.- Core Selection in the SOC Test Design-Flow.- Defect-Aware Test Scheduling.- An Integrated Technique for Test Vector Selection and Test Scheduling under ATE Memory Depth Constraint.

Notă biografică

Dr. Erik Larsson is an assistant professor at Linköpings University in Sweden, and he is an active member of the IEEE Testing and Circuits & Systems societies

Caracteristici

System perspective to SOC test design. Overview of test problems and their modeling Test scheduling overview, extensive reference list Applicable for Master students and PhD-students working in the test field. Could also be good for researchers and professors who would like to get into the area of SOC testing, also for persons in the field who want some references Includes supplementary material: sn.pub/extras