Testability Concepts for Digital ICs: The Macro Test Approach: Frontiers in Electronic Testing, cartea 3
Autor F.P.M. Beenker, R.G. Bennetts, A.P. Thijssenen Limba Engleză Hardback – 30 noi 1995
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Specificații
ISBN-13: 9780792396581
ISBN-10: 0792396588
Pagini: 212
Ilustrații: IX, 212 p.
Dimensiuni: 170 x 244 x 14 mm
Greutate: 0.5 kg
Ediția:1995
Editura: Springer Us
Colecția Springer
Seria Frontiers in Electronic Testing
Locul publicării:New York, NY, United States
ISBN-10: 0792396588
Pagini: 212
Ilustrații: IX, 212 p.
Dimensiuni: 170 x 244 x 14 mm
Greutate: 0.5 kg
Ediția:1995
Editura: Springer Us
Colecția Springer
Seria Frontiers in Electronic Testing
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
1 Introduction.- 1.1 The Main Topic.- 1.2 Test Objectives.- 1.3 Definition of Testability.- 1.4 Problem Statement: Strategies and Requirements.- 1.5 Outline.- 2 Defect-Oriented Testing.- 2.1 Reason.- 2.2 Defects and Faults.- 2.3 Defect-Fault Relationship: Inductive Fault Analysis.- 2.4 Fault-Defect Relationship: Process Monitoring Testing.- 3 Macro Test: A Framework for Testable IC Design.- 3.1 Introduction to the Macro Test Philosophy.- 3.2 Testability Synthesis within the Macro Test Concept.- 3.3 Integration of Macro Test into a Design & Test flow.- 3.4 Summary of Essential Macro Test Items.- 4 Examples of Leaf-Macro Test Techniques.- 4.1 Defect Modeling and Test Algorithm Development for Static Random Access Memories (SRAMs).- 4.2 Built-in Self-Test for Static Random Access Memories.- 4.3 Leaf-Macro Testability Study Aspects.- 5 Scan Chain Routing with Minimal Test Application Time.- 5.1 Leaf-Macro Access.- 5.2 Introduction to Scan Chain Routing.- 5.3 Scan Test Application Protocol.- 5.4 Scan Chain Routing Problem Formulation.- 5.5 Scan Chain Routing Cost Model.- 5.6 Scan Chain Routing Problem Complexity.- 5.7 Routing of Scan Registers into a Single Scan Chain.- 6 Test Control Block Concepts.- 6.1 Introduction.- 6.2 Test Control Block Requirements.- 6.3 Test Controller Architectures.- 6.4 Relation between a Test Control Block and Test Plans.- 6.5 Test Control Block Design Requirements.- 6.6 Optimal Test Control Block implementation.- 6.7 Test Control Block Design Example.- 6.8 Distributed Test Control.- 7 Exploiting Parallelism in Leaf-Macro Access.- 7.1 Introduction.- 7.2 Levels of Parallelism.- 7.3 Formal Definitions of Resources, Resource Compatibility and Parallelism.- 7.4 Test Compatibility Graphs.- 7.5 Resource Allocation versus Test Assembly.- 7.6 AlgorithmicImplementation and Experimental Results.- 8 Timing Aspects of CMOS VLSI Circuits.- 8.1 Introduction.- 8.2 Timing Models of Latches and Flip-Flops.- 8.3 Timing of Data Transfers.- 8.4 Clock Drivers.- List of Symbols and Abbreviations.- References.