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Verification by Error Modeling: Using Testing Techniques in Hardware Verification: Frontiers in Electronic Testing, cartea 25

Autor Katarzyna Radecka, Zeljko Zilic
en Limba Engleză Hardback – 30 noi 2003
1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be “imminently doable” by Intel fellow J. Crawford at Microprocessor Forum in October 2002 [40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs is a must. Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In general, however, a typical product cycle includes few milestones. An idea for a new product starts usually from an - depth market analysis of customer needs. Once a window of opportunity is found, product requirements are carefully specified. Ideally, these parameters would not change during the design process. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design.
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Specificații

ISBN-13: 9781402076527
ISBN-10: 1402076525
Pagini: 236
Ilustrații: XV, 216 p.
Dimensiuni: 155 x 235 x 18 mm
Greutate: 0.55 kg
Ediția:2003
Editura: Springer Us
Colecția Springer
Seria Frontiers in Electronic Testing

Locul publicării:New York, NY, United States

Public țintă

Research

Cuprins

Boolean Function Representations.- Don’t Cares and Their Calculation.- Testing.- Design Error Models.- Design Verification by At.- Identifying Redundant Gate and Wire Replacements.- Conclusions and Future Work.

Recenzii

From the reviews:
"This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. … The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004)