Cantitate/Preț
Produs
Total produse
Vezi coșul
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test de Andrei Pavlov

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test: Frontiers in Electronic Testing, cartea 40

Autor Andrei Pavlov, Manoj Sachdev
en Limba Engleză Hardback – 21 iun 2008
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.
Citește tot Restrânge

Toate formatele și edițiile

Toate formatele și edițiile Preț Express
Paperback (1) 99502 lei  43-57 zile
  SPRINGER NETHERLANDS – 28 oct 2010 99502 lei  43-57 zile
Hardback (1) 100102 lei  43-57 zile
  SPRINGER NETHERLANDS – 21 iun 2008 100102 lei  43-57 zile

Din seria Frontiers in Electronic Testing

Preț: 100102 lei

Preț vechi: 122075 lei
-18% Nou

Puncte Express: 1502
Preț estimativ în valută:
19156€ • 19878$ • 16012£

Carte tipărită la comandă

Livrare economică 17-31 martie

 Adaugă în coș

Wish list
Gift list
Am citit!
Adaugă în listă
Preluare comenzi: 021 569.72.76

Specificații

ISBN-13: 9781402083624
ISBN-10: 1402083629
Pagini: 212
Ilustrații: XVI, 194 p.
Dimensiuni: 155 x 235 x 19 mm
Greutate: 0.48 kg
Ediția:2008
Editura: SPRINGER NETHERLANDS
Colecția Springer
Seria Frontiers in Electronic Testing

Locul publicării:Dordrecht, Netherlands

Public țintă

Research

Cuprins

and Motivation.- SRAM Circuit Design and Operation.- SRAM Cell Stability: Definition, Modeling and Testing.- Traditional SRAM Fault Models and Test Practices.- Techniques for Detection of SRAM Cells with Stability Faults.- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques.

Notă biografică

Prof. Sachdev has authored several successful books with Springer

Textul de pe ultima copertă

As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions.
Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired.
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.

Caracteristici

Gives a process-aware perspective on SRAM circuit design and test Provides detailed coverage of SRAM cell stability, stability sensitivity and analytical evaluation of Static Noise Margin Introduces the concept of stability fault modelling Provides an Overview of specialized Design for Testability techniques for SRAM stability test Addresses soft-error considerations of SRAM design